TSMC reiterated its long-known stance on next-generation High-NA EUV lithography tools at its European Technology Symposium in Amsterdam. The company does not require these highest-end lithography systems for its next-generation process technologies, including A16 (1.6nm-class) and A14 (1.4nm-class) process technologies. To that end, TSMC will not adopt High-NA EUV tools for these nodes.
“ People seems to always interested when TSMC going to use High-NA, I think our answer is very simple,” said Kevin Zhang, Deputy Co-COO and Senior Vice President of Business Development and Global Sales, at the event. “Whenever we see High-NA will provide meaningful, measurable benefit, we will do it. With A14, the enhancement I talked about earlier is very substantial without using High-NA. So, our technology team continues to find a way to extend the life of current EUV while harvesting the scaling benefit.”
TSMC’s A14 process relies on the company’s second-generation nanosheet gate-all-around transistors, along with a new standard cell architecture. According to TSMC, A14 provides up to 15% higher performance at the same power and complexity, or alternatively, 25% to 30% lower power consumption at the same frequency. In terms of transistor density, A14 achieves a 20% increase compared to N2 for mixed logic/SRAM/analog configurations and up to 23% when it comes to pure logic.
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Such performance, power, and transistor density increases represent the so-called ‘full node advantage’, and yet, TSMC does not need next-generation High-NA EUV lithography tools to produce chips with predictable yields and desired performance and power characteristics on its A16 and A14 process technologies. One should keep in mind that TSMC’s A16 is essentially N2P with a Super Power Rail (SPR) backside power delivery network. As TSMC does not need High-NA EUV tools for N2 and N2P, it will not need them for A16 either. By contrast, A14 is an all-new node that will be used for mass production in 2028, so the fact that TSMC does not need High-NA for this one is quite remarkable.
When asked whether A14 heavily relies on multi-patterning, Zhang responded that he could not comment on specifics, but said that TSMC’s technology team had found a way to produce chips on a 1.4nm node without using High-NA EUV tools that provide an 8nm resolution compared to a 13.5nm resolution of Low-NA EUV systems.
“This is a great innovation from our technology team,” said Zhang. “As long as they continue to find a way, obviously, we do not have to use High-NA EUV. Eventually, we will use it at some point. It is just so we need to find a right interception point, provide the maximum benefit, maximum return on investment.”
It is noteworthy that TSMC’s A14 will be succeeded by A14 with SPR backside power delivery in 2029, and it does not appear that the foundry will require High-NA EUV tools for this iteration either. To that end, it looks like, unlike Intel, which is set to start using next-generation EUV lithography machines with its 14A manufacturing technology to reduce the number of EUV exposures (read: multipatterning) and process steps in 2027 – 2028, TSMC has no plans to use High-NA EUV for mass production until at least 2030, or perhaps even later.
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